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IXP NPU
Software Methodology:
Experience Generating a High Level Microcode Architecture That Is
Both Flexible and Yet High Performance
Comm Logic Design, Inc. believes in following the Intel microACE,
or Intel Portability Framework where ever possible. We believe that
Intel provides a quality structure within which
many applications can be built. In addition working within the portability
framework provides the ability to leverage an extensive code base provided
by Intel and third party developers, which aids in reducing time to market and
technical risk.
At times we find that the Intel portability framework falls short
in terms of functionality and / or performance. However, we believe
it is usually worthwhile to enhance the portability framework
and the code in the Intel SDKs to address these shortcomings,
rather than invent a custom solution for our clients.
Experience with Intel IXA SDK
through version 4.1 Including the Following
Modules and Functionality
Comm Logic Design has followed the evolution of
the Intel IXA SDK 3.0 through
4.1. We have worked extensively with nearly all of the intervening
PR releases. All of our existing IXP2xxx projects have been migrated to the FCS
release of SDK 4.1.
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Ethernet and POS Receive and Transmit |
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AAL-5 SAR:
Comm Logic Design hasn't yet
developed a project utilizing Intel's AAL-5
segmentation and reassembly code from the IXA SDK. However, we have
read the code and are familiar with its characteristics and hardware
requirements. |
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802.3 VLAN:
Comm Logic Design has a client project that contains VLAN functionality
including some of the code related to VLANs included in the IXA SDK. |
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Fast table searching:
Nearly all of Comm Logic Design's projects have involved some form
of fast table searching. We have developed implementations that
utilize Microcode
table searches, and in some circumstances offload searches to Network Search Engines (NSE) or TCAMs. Some of our microcoded
searches have make use of the hardware hash units
provided in the IXP2xxx
to speed hash table based searches. Others involve modifying
data structures used in C based applications (e.g. Snort) for high
speed use on the IXP2xxx microengine. |
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Fast packet classification:
Again nearly all of our designs perform some form of packed classification
prior to performing forwarding, switching, or routing decisions. We utilize
the code provided by the IXA SDK wherever possible. Often we
enhance, modify or remove portions of the SDK code, to match a client's requirements.
Also, at times we have offloaded classification functions to external
co-processors, (e.g. the IDT 2500 CIE) and have used the coprocessor classification
results prior to making switching, routing, or
inspection decisions. |
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Packet encapsulation / decapsulation:
Some of our client applications require packet encapsulation
and
decapsulation along the datapath. We have supported MAC layer, VLAN,
and tunneling applications. We have also developed multicast applications,
that involve rewriting a header on each multicast copy which is somewhat
similar to encapsulation. |
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Traffic policing:
We haven't
developed a policing application on the IXP2xxx. However, we
have written a traffic shaper utilizing the framework provided by the
queue manager and packet shaper microblocks in the IXA SDK
3.1. Intel's shaper and queuing architecture is rather complex,
but given our experience with shapers, traffic
policing development is certainly within our
capability. |
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