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FPGA Projects:

The following list provides a brief introduction into a few of the FPGA projects Comm Logic Design has developed recently.  In each case, our team was solely responsible for the successful implementation and delivery of each FPGA project listed.

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Xilinx Virtex-7 Quad 100G Ethernet Input Aggregation

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Xilinx Virtex-7 Multi-Hundred-Gig-Plus Ethernet Interlaken Bridges

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Altera MAX II Low Pin-Count (LPC) Intel Interface

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Xilinx Virtex-5 Flow Acceleration SubsysTem packet processors

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Xilinx Virtex-II Pro DDR SDRAM cache controller.

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Altera Stratix-II TCAM Reference Platform

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Xilinx Virtex-II Pro Embedded PowerPC based designs using Xilinx EDK.

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Xilinx Spartan-3 MicroBlaze Embedded Processor designs using Xilinx EDK.

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Silicon Data Base Controller with deep packet inspection capability built into a Xilinx Virtex-II Pro integrating Network Search Engine (TCAM) support, DDR DRAM interface, QDR-II / LA-1 multi-context NPU interface, Embedded PowerPC subsystem for RAM/ALU, Aurora / multi-channel bonded Rocket IO combined to implement a stateful database in silicon.

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10G throughput, 64GByte DDR SDRAM Caching Sector Controller architectural development for mid-level Storage Area Network appliance.

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ATM long-range wireless base station base-band processor and MAC FPGA built into a Xilinx Virtex-II Pro.  Design was a port of an existing design, with extensive new functionality added.  Included Utopia interface, SDRAM controller, SAR, PowerPC interface, arbiters, framers, deframers and timing logic.

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SPI4.2 to SPI-3 to Backplane bus bridge and switch used in an Intel IXP2800 based Network Security application. Design used Xilinx SPI4.2 and SPI3 cores.

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Intel IXP2800 QDR-II / LA-1 SRAM co-processor interface to Network Search Engine (CAM), Content Inspection Engine (Classifier) multi-accesses sequencer with Dual Port RAM DMA engines.

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Decanonicalization and Normalization Network Search Engine Preprocessor for expedited search throughput.

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POS, Ethernet, IP, TCP, UDP, ICMP Protocol Manipulation / Checksum Calculations, Packet Buffers for Intel IXP1200 and cut-through / bypass interfaces.

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OC48 Packet-Over-Sonet Receive FPGA, IP protocol manipulation, MPLS, Layer 2/3/4 including IPv6 protocol field extraction / checksum generation, with interface to Intel IXBus.

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Gigabit Ethernet Receive FPGA, IP protocol manipulation, MPLS, Layer 2/3/4 protocol field extraction / checksum generation, with interface to Intel IXBus.

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OC48 Packet-Over-Sonet Transmit FPGA, IXF6048 Utopia 3 bus interface, "mpacket" buffering, with interface from Intel IXBus.

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Gigabit Ethernet Transmit FPGA, multi-port IXF1002 and IXF1104 Framer interface with "mpacket " buffering, with interface from Intel IXBus.

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Content Inspection Engine (Classifier) co-processor design augmenting ClassiPi functionality.

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Dual 32bit Intel IXP-bus interfaces, backplane interfacing, "mpacket" buffering and switching, "mpacket" routing.

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Image pixel processor for IC Mask Printer used to manufacture silicon wafers.

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SDRAM memory virtualization and mirroring controller for use in an Intel IXP1200 packet forwarding system.

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Sustaining Engineering for an ATM wireless link Media Access Controller (MAC) to Utopia interface.
 

FPGA Device Expertise:

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Xilinx Virtex-7, Virtex-6, Virtex-5, Virtex-4, Virtex-II Pro, Virtex-II, Virtex-E, Spartan-6, Spartan-3, Spartan-2, Coolrunner CPLDs

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Altera Stratix-V, Stratix-III, Stratix-II, Stratix, Apex20K, Flex10K, Flex8K, Flex6K, Max9K, Max7K, MAX-II

 

Last changed: 06/05/2012 10:46:55 Copyright 2003 through 2012 Comm Logic Design, Inc.